The present invention relates to a non-volatile memory and a write method of the same, and more specifically, to a flash memory that is electrically erasable/writable and a write method of the same.
Recently, in a semiconductor integrated circuit device (LSI) such as an ASIC, a logic combined flash memory is being widely used. The flash memory is a non-volatile memory, in which data is entirely erased and written electrically, and holds data even when there is no power since charges are maintained in an electrically separated region called a floating gate, which is embedded in a gate oxide film. There is a demand for shortening the erase/write time in such flash memory.
Writing to the flash memory consists of two operations, erasing and programming. Erasing is an operation for reducing a threshold value of a memory cell (cell transistor), programming is an operation for increasing the threshold value, and generally, the state in which the threshold value is low corresponds to data “1”, and the state in which the threshold value is high corresponds to data “0”. Normally, erasing performs total erasing in a memory unit having a certain size and referred to as a sector, and programming performs writing for each cell (bit) unit.
Conventionally, a flash memory (e.g., refer to Japanese Laid-Open Patent Publication No. 5-342892) in which erasing is performed in any single bit is known. In the configuration disclosed in Japanese Laid-Open Patent Publication No. 5-342892, a source line connected to each cell constituting the cell array is arranged separately from each other for each column unit cell. By applying high voltage to a source line externally specified by an address and applying a negative voltage to a word line, an arbitrary bit within the cell array is erased.
Other examples include a plurality of cells connected to the same word line that is erased in byte units (e.g., refer to Japanese Laid-Open Patent Publication No. 6-251594). In the configuration disclosed in Japanese Laid-Open Patent Publication No. 6-251594, the source line connected to each cell is arranged so as to be shared between adjacent cells in the column direction. In the same manner as in Japanese Laid-Open Patent Publication No. 5-342892, by applying high voltage to a source line externally specified by an address and applying negative voltage to the word line, a plurality of cells are entirely erased in byte units.
In Japanese Laid-Open Patent Publication Nos. 5-342892 and 6-251594, erasing of cells is performed by eliminating electrons from the floating gate using the FN (Fowler-Nordheim) tunnel current flowing between the source and floating gate. On the other hand, the programming is performed by injecting electrons (hot electrons) into the floating gate using the avalanche breakdown phenomenon.
However, hot electrons have a low generation efficiency, and, for example, the current flowing to the floating gate is only about a few pA with respect to the drain current of about 100 μA flowing during programming. Thus, a problem in which the current efficiency is low, and the current consumption increases during program occurs.
Recently, a method for injecting electrons into the floating gate using the FN tunnel current flowing between the channel-floating gate for programming in addition to erasing has been proposed in response to the demand for low power consumption (e.g., refer to Japanese Laid-Open Patent Publication No. 11-177068). In case of performing programming with the tunnel current, the current efficiency is improved by about three digits compared to when hot electrons are used.